#104 – David Patterson: Computer Architecture and Data Storage — Summary & Takeaways

At a Glance

David Patterson, Turing Award winner and professor of computer science at UC Berkeley, reflected on his career's core contributions in an interview: the RISC processor architecture (currently used in 99% of new chips) and the co-creation of the RAID storage system. He discussed the differences between RISC and CISC architectures, emphasizing the artistry of simplified instruction set design, and introduced the RISC-V open standard instruction set architecture. Additionally, he explored how machine learning is changing computer design, new ML benchmarks, the prospects of quantum computing, the current state of Moore's Law, and the evolution of RAID storage. Patterson noted that the success of RISC architecture stems from the design philosophy of "simplicity is beauty," and that the open standard RISC-V is expected to further drive chip innovation.

Theme 1: RISC vs. CISC – Why Simpler Instruction Sets Win

David Patterson argues that the core advantage of RISC architecture lies not in the number of instructions, but in the significant reduction of cycles per instruction (CPI), which is the key to its performance superiority over CISC.

Patterson describes his experience with John Hennessy in the 1980s as "radicals" promoting the RISC concept. At that time, the industry widely adopted Complex Instruction Set Computing (CISC), believing that "powerful instructions" could simplify software writing. However, Patterson's team proposed that for rapidly evolving microprocessors, a simpler instruction set was more appropriate.

Historical Context: The CISC design philosophy held that complex instructions such as "polynomial division" or "list sorting" could simplify programming, but Patterson points out that compilers struggled to effectively utilize these complex instructions, resulting in overly complicated hardware design and underutilized instructions.
Mechanism Breakdown: Patterson introduces a key formula: Program execution time = Number of instructions × Cycles per instruction × Clock cycle time. He explains that although RISC executes about 25%–50% more instructions than CISC, its cycles per instruction (CPI) is only about 1/5 of CISC's (2 cycles for RISC vs. 10 cycles for CISC), thereby delivering a 3–4x performance improvement.
Historical Turning Point: Patterson recalls that the concept "sparked heated debate" in 1982, but by 1984, with the introduction of quantitative analysis methods, the industry generally accepted the technical advantages of RISC. He notes that Intel's CISC architecture (x86) survived commercially through hardware dynamic translation (converting x86 instructions into internal RISC instructions in real time), but this process increased chip area and power consumption.
Reader Note: As a co-founder of RISC, Patterson's narrative carries an obvious "insider" perspective; readers should note his emphasis on his own contributions.

Theme 2: RISC-V — The Potential of Open Standards and Market Landscape

Patterson believes that the RISC-V open standard instruction set architecture has the potential to become the most popular instruction set in the future, particularly in the IoT and cloud service sectors, though smartphones face higher barriers due to ARM's binary compatibility.

Patterson notes that RISC-V is a project initiated by the Berkeley team in 2010, aiming to learn from the mistakes of past RISC architectures (such as MIPS, ARM, SPARC, etc.) and adopt an open licensing model (BSD license).

Market Landscape Analysis: Patterson divides the current market into three major segments:
Cloud Services: Almost 100% dominated by x86 (Intel). However, cloud service providers (such as Google, Amazon, Alibaba) control the software stack, and Patterson believes they may shift to RISC-V.
Smartphones: Dominated by ARM, where end-user software is distributed in the ARM instruction set (binary) form, creating a "binary compatibility" barrier. Patterson considers this the most difficult area for RISC-V to penetrate, but if the RISC-V ecosystem matures, it may take a decade to achieve the transition.
Internet of Things (IoT): Embedded devices lack a dominant architecture, and device manufacturers control the software stack. Patterson views this as the market where RISC-V is most likely to penetrate rapidly in the near term.
Design Philosophy Highlights: Patterson particularly emphasizes RISC-V's "core subset + optional extensions" design: the core instruction set consists of only about 40 instructions, allowing software to run based solely on this; optional extensions (such as math acceleration, vector processing, etc.) can be added as needed, avoiding the problem of "bloat" that traditional instruction sets accumulate over time. He describes it as "keeping the instruction set as slim as a teenager."
Data Support: Patterson notes that attendance at the RISC-V Summit grew from 50 people in 2015 to approximately 1,700 in December 2019, reflecting its rapidly expanding ecosystem.

Theme 3: The Current State of Moore's Law and the New Era of Computing

Patterson clearly states that Moore's Law (transistor count doubling every two years) is no longer valid, but this is not the end of computing — it marks the beginning of a "new golden age" pivoting toward domain-specific accelerators, particularly machine learning accelerators.

Patterson directly refutes Jim Keller's view that "Moore's Law is still alive," calling it "marketing."

Quantitative Evidence: Patterson points out that, according to the definition of Moore's Law, if it were still in effect, DRAM chips and Intel microprocessors from six years ago should have eight times the transistor count of today's — which is not the case. He notes that transistor costs are no longer declining and may even be rising, further undermining the old logic of Moore's Law.
Historical Comparison: In the 1980s–1990s, computer performance doubled every 18 months, and users voluntarily upgraded devices due to performance gains. Today, Patterson says he only buys a new computer when "the old one breaks," because performance improvements have slowed to just a few percentage points per year.
New Path: Domain-Specific Architecture: Patterson argues that the solution is to design accelerators for specific application domains, and machine learning (ML) presents a perfect opportunity. He explains:
The core computation of ML is matrix multiplication, an area hardware designers excel at.
General-purpose processor performance has stalled, but ML accelerators (e.g., Google TPU, Habana chips) can deliver significant performance gains.
He believes this trend will usher in a "Software 2.0" era, where programs are driven by data rather than manually written, further increasing demand for specialized computing power.
Reader's Note: Patterson uses the "death" of Moore's Law as a "warning/call to action" to drive industry change. His view carries a clear educational and directional intent, rather than being purely objective and neutral.

Theme 4: Benchmarking, Quantum Computing, and RAID – Lessons and Outlook

Patterson emphasizes that benchmarking is a key tool to quantify technological progress and eliminate "false claims," citing the success of MLPerf. At the same time, he holds a cautious view on quantum computing, arguing that its commercial application will not materialize until at least 2030.

MLPerf Benchmark: Patterson co-created MLPerf, aimed at providing fair and reproducible benchmarks for ML hardware. He notes that the startup Habana (later acquired by Intel for $2 billion) was selected by Intel as its future product line due to outstanding MLPerf results, while Nirvana, another Intel acquisition, had its product line discontinued because it did not publish MLPerf results, serving as a failure case of "impressive hardware but missing software stack."
Quantum Computing: Patterson references two national reports, concluding that practical, error-corrected quantum computing is still about 10 years away (expected around 2030). He likens it to "nuclear fusion" – a bright long-term prospect but not something to rely on in the short term. He also notes that quantum computing will be a "datacenter-scale" application, requiring near absolute zero operation, and that a "quantum cellphone" is impossible.
RAID Storage: Patterson recalls co-authoring the 1988 paper "RAID" with Randy Katz and Garth Gibson. The core idea: replace a single large IBM disk with multiple cheap PC disks (about 40 at the time), solving reliability issues through redundancy (RAID). He points out that RAID is not only cheaper and faster (due to parallelism), but also achieves higher reliability than a single high-end disk through redundancy (a single disk failure would cause data loss, whereas RAID can tolerate multiple disk failures). Today, the RAID concept has been extended to the flash memory (SSD) domain.

Targets Mentioned

Target	Guest Attitude	Key Data
Intel (x86)	Technical assessment: CISC architecture disadvantage; Commercial assessment: successful but reliant on hardware translation	Dominates PC and data centers; architecture power and area efficiency lower than RISC
ARM	Evaluated as a "highly successful RISC architecture", but "proprietary"	Dominates global mobile phone chips; billions of units shipped annually; Apple designs its own ARM cores
RISC-V	Bullish, believed likely to become the most popular instruction set	Core instruction set about 40 instructions; December 2019 summit attendees 1,700 (2015: 50)
Habana (acquired by Intel)	Positive case, successful due to complete software stack	Intel acquired for $2 billion; excellent MLPerf results
Nirvana (acquired by Intel)	Negative case, failed due to lack of software stack	Intel canceled product line; no MLPerf results published
Google (TPU)	Mentioned positively, as a benchmark ML accelerator	Co-founded MLPerf
Nvidia	Mentioned as MLPerf participant	No specific data provided
Apple (A-series chips)	Positive assessment of its self-designed ARM core capabilities	Self-designed chips outperform other ARM vendors
IBM	Mentioned positively: early RISC promoter; RAID paper reviewer	Controlled the large disk market in the 1980s

Memorable Judgments

1. Patterson argues that the core advantage of RISC is that its cycles per instruction (CPI) is as low as about 1/5 of CISC, rather than a smaller number of instructions — although RISC requires executing 25%-50% more instructions, the faster execution speed yields a 3-4x performance improvement.

2. Patterson explicitly states that 'Moore's Law (transistor doubling every two years) is no longer valid', and uses the quantitative evidence that DRAM/Intel microprocessor transistor counts have not achieved an 8x increase over the past six years to refute Jim Keller's 'marketing' view.

3. Patterson believes that machine learning (ML) accelerators will be the primary avenue for computing performance improvement over the next decade, because general-purpose processor performance gains have dropped to a few percentage points per year, and ML core computation (matrix multiplication) is an area where hardware excels.

4. Patterson's proposed design philosophy of 'RISC-V core subset + optional extensions' aims to avoid the drawback of traditional instruction sets 'expanding with age' — the core has only 40 instructions, software can run solely on this basis, but acceleration extensions can be enabled as needed.

5. Patterson cites the original motivation for RAID: replacing a single large IBM mainframe disk with 40 inexpensive PC disks, achieving higher reliability through redundancy (a single large disk failure loses data, while RAID can tolerate multiple failures), while improving performance and reducing cost.

6. Patterson argues that without benchmarks, progress in a field cannot be measured, and cites the successful case of MLPerf — Habana was acquired by Intel for $2 billion due to outstanding MLPerf results, while Nirvana's product line was canceled for not disclosing results.

7. Patterson's judgment on quantum computing: practical use still requires about 10 years (2030), analogizing it to 'nuclear fusion' — the prospects are bright but cannot be relied upon in the short term, and it will be a 'data-center-level' application, with no possibility of a 'quantum phone'.

8. Patterson's measure of a 'successful life': he cites the view of colleague Randy Katz — 'It's not the number of zeros in your bank account; it's the number of inches in your New York Times obituary' — and emphasizes that the impact on others (through education, mentoring, team building) outweighs papers or money.